Optimizing decoupling capacitors to cut down conducted emissions in a DC–DC buck converter using a differential evolution algorithm.

Abstract

In this study, the conducted emission levels of a circuit containing a nonlinear load and equipped with a DC–DC buck converter module have been predicted using modeling and simulation methods. Additionally, the number and values of decoupling capacitors used in this circuit have been optimized through a differential evolution algorithm. In this context, two different PCB designs, with and without decoupling capacitors, have been developed. First, the experimental EMC test of the configuration without capacitors has been conducted, followed by the CE test simulation using the SPICE model. When comparing the results, the highest CE level has been found to be 85.63 dBμV at 202 kHz in the experimental results, and 85.9036 dBμV in the simulation results. Subsequently, an optimization based on a differential evolution algorithm has been performed using co-simulation between MATLAB/Simulink and PSpice. The obtained capacitor values have been applied to the physical circuit, and EMC tests have been repeated. When comparing these test and simulation results, the highest CE level has been measured at 82.49 dBμV at 210 kHz in the experimental results, and 81.802 dBμV in the simulation results. These findings suggest that optimizing decoupling capacitors can improve EMC performance. The research results demonstrate that predicting conducted emission tests through computer-based simulations and design optimization with a differential evolution algorithm is possible.