Volume 2, No. ı , 1987 Journal of the Faculties of Engineering of Uludağ University FLOATING ADC METHOD* FOR SERIES- PARALLEL A/D CONVERSION Ergür TÜTÜNCÜOGLU** ABSTRACT In this paper, a {u /Iy integrab/e 8 bit series-paraUel AD co nuerter based on a new "floating ADC" principle is presented. Cross-plot testst o f the experimental conuerter reuealed that the d if{erential nonlinearity o f the 8 bit system will be less than ± ~ LSB {or an analog input uo ltage of {Vp p· A conuerter o{ this type pro uides a good alternatiue to the all paral/el system at sampling frequencies up to 100 M Hz . when chip size and power dissipation must be reduced. INTRODUCTION Several problems arise when attempting to apply the concept of series-paraliPI AD canversion to achieve the greater resolution required for wordlength of 8 bit , at the sampling rate of 100 MHz ı. First of all, the accuracy of the system is mainly determined by the OAC used in the circuit. Moreover, the circuits which drive the differential amplifier (Dif. A.) through .the (+) and (-) inputs, respectively, are not identical and result in a tem- perature dependent o ffse t voltage at the output of the amplifier. This offset voltage causes a considerable error degrading the overall accuracy of the ADC (Fig. 1 ). On the other hand, digi tal sampling can be applied with the use of latched comparators to increase the canversion speed to the 100 MHz range which cannot be offered by the available sample and hold circuits. In this case thPre is no need for a high speed and high accuracy sample and hold circui t but Olh' needs a high precision analog delay circuit in order to compensate for the signal t ransmission detay in the first ADC and OAC, i.e. (T1 + T2 ) , (Fig. 1). * This work has been sponsored by the "Fonds z ur Förderıuı;: der wissell · schaftlichen Forschung " Vienna, Austria. Projekt Nr. S22/ 11. ** Pro f. Dr.; Uludağ ü niversitesi, Bursa Mühendislilz Fa/zültesi. -1- OAConv . } ır.;ıı Fig. 1 - Series·parallel canverter with the sample and hold circuit In hipolar technology, it is quite difficult to realize such an analog delay circuit giving precisely the delay of (T 1 + T 2 ) within the desired bandwidth. Thus, to eleminate this delay circuit and solve the offset problem of the diffe- rential amplifier, a new "Floating ADC" principle is developed and applied. . THE FLOATING ADC PRINCIPLE In this series-paraUel canversion principle the second ADC is floating over the intervals between the quantization levels of the first ADC (Fig. 2), and is connected to the appropriate interval corresponding to the momentary value of the analog input signal without waiting for the appearance of. the MSB output. It will be seen that no additional analog delay-circuit is necessary for signals com- roonly encountered in practice, when the determination of the interval and the connection of the second ADC is realized with sufficiently fast circuitry. Ist ADC 2nd " rloating" AOC ~ ! t ıs levels } (HSB•l ) -_ ___...,----- T7 '- -,ıı.:.ı.----- } LSB - - 8 bit 1 1 S bit 2SS l e vels ~ -fıs ı;v:lı-----} (HSB.J > in total H S B '7 bleivt els 1/2 level shift ed Fig. 2 - The "floating ADC" principlc applicable in series·parallel canversion method The black diagram of the new series-paraUel ADC based on the "Floating ADC" principle is given in Fig. 3, where the first ADC (Center block) which is a fully paraHel digitally sampled 3 bit device, differs from a conventional one only in that it incorporates a (± 1) circuit. - 2- Aııa loq l npul lle lay r -+- r -+- T 1 2 3 Fig. 3 - Block diagram of the new series-paraHel ADC based on the "floating ADC" principle The second ADC (upper block) is also a digitally sampled 5-bitparallel canver- ter having (± 1) command outputs. This co.nverter has additional 15 levels above and below the normal 32 Levels, respectively. These 62 levels are combinedin such a way as to result into normal 5-bit LSB at the output of the canverter (Fig. 2 and 3). Second ADC encoding levels are given in Fig. 4 where(± 1) command levels are indicated. t~ = ----r F-'=ıs ı ,;= · • _ _MSB+l __ j l Coımıand ı "- 1 Wi ndo w fi rst AOC 32 No Change levels Comp. i n HS 8 (n) "' o . . 7 HSB- 1 - 1 CoomıanÇ __j ___ _ı_ Fig. 4 - 2 nd ADC encoding !eve ls -3- The blocks which deliver the input signal of the 2 nd. ADC (input connection circuits of the 2 nd. ADC), Fig. 3, exhibit following significant differences in com- parison wi th the system in Fig. ı : i.- The inputs of the 2 nd. ADC driving blocks (Fig. 3) are paraUel with inputs of ı st. ADC, so that they are both fed by the same analog and 7 reference voltages, which give an equally spaced 7 value scale (0-7). ii.- The 2 nd. ADC driving blocks consist of 8-differential amplifiers and 8- "ı st Encoder + analog switch" circuits, each corresponding to one quan- tization !eve! (encoding !eve!) of the ı st. ADC (from zeroto seven). iii.- The analog switches can be realized in a differential form which results in a less temperature dependent offset voltage than that of the unsym- metrically driven differential amplifier "Dif. A" of Fig. 1. iv.- Logic input signals (LS) of the ı st. encoder circuits which activate their analog switches are delivered by the 7 -outputs of the Iatebed comparators (C+ DSH) of the ı st. ADC. That gives the possibility to control the analog switches without waiting until the 3 bit MSB value becomes available at the output. The encoding levels of the ı st and 2 nd ADC's are given in Fig. 2. Second ADC encoding levels are redrawn in Fig. 2 in detail. The logic output signals from seven (C+ DSH) blocks of the ı st. ADC give a coarse representation of the analoginput voltage: All blocks with reference voltages below the input voltage produce a logic "ı". That information is used both by the ı st. and 2 nd. encoders (Fig. 3) to determine the level which is passed by the ana- loginput signal. At the same time, all differences between the analog signal and the reference voltage levels (O - 7) are available at the outputs of the differential amplifiers (Dif. A). As soon as the ı st. encoder activates the correct analog switch corresponding to the !eve! passed, the related difference is immediately applied to the input of the 2 nd. In other words, the 2 nd. ADC is connected to the appropriate window deter- mined by the instantaneous value of the analog input signal. Evidently the 2 nd. ADC isa "Floating ADC" and bence this technique can be called as the" Floating ADC" method. EXPERIMENTAL 6 BIT CONVERTER An experimental 6 Bit ADC has been built consisting of two cards, one con- taining the 3 bit "ı st. ADC" and "input connection circuit of the 2 nd. ADC", the second containing the 3 bit "2 nd. ADC". The complete circuitry has been realized using Schottky TTL comparators: 25 X (NE 529 N); transistor arrays: ı5 X (CA 3ı27 E), 4 X (CA 3046), 4 X (CA 3ı02), JK flip-flops: 8 X (74Sl12) and NAND gates: 9 X (74800), 7 X (74S10). TESTING By superimposing a triangular-wave signal (V ac> on a de. voltage (V de) applied to the input of the ADC under test, we can sweep some of the ADC output -4- codes of interest on the oscilloscope screen (Fig. 5 ). \ ınpul Fig. 5 - Set·up for the dynamic cro ss·plot test Using a dynaınic cross-plot test the set-up of Fig. 13 enables us to detennine the analog values corresponding to the transitions and the center of each code quantization level, which in tum pennits detennining device nonlinearity and diffe- rential nonlinearity. For this purpose, the two least significant bits are decoded by a simple R-2R DAC. This decoded signal is fed to the vertical input of the oscillos- cope while the triangular-wave signal is applied to the horizontal input of the scope. The experimental 6 bit ADC has been tested and results of the cross-plot test are as follows : i.- There was no missing code through the whole analoginput range. ii.- Transfer characteristic was completely monotonic. iii.- With a 1 VP P' 10 kHz triangular-wave input signal at 25 MHz sampling rate, maximum differential nonlinearity was found to be 0,1 LSB. CONCLUSIONS 1 - A maximum differential nonlinearity of 0,1 LSB pennits to increase the number of the 2 nd. ADC bi ts from 3 to 5 in order to have an 8 bit con- verter. In this case it can be estimated that the differential nonlinearity will not be greater than 0,4 LSB giving an acceptable SIN ratio for an 8 bit ADC. On the other hand, if an analog in put signal of 2 Vp p is used, differential nonlinearity further reduces to 0,2 LSB resulting in a better SIN ratio. 2- If a high speed hipolar process is applied (fT == 3 GHz for lE == lmA), the integrated 8 bit ADC can easly operate at a sample rate of 100 MHz owing to the high speed of the ECL mode circuitry used. 3 - There is no need for a precise analog delay circuit in the device. - 5 - 4 - Although the number of quantization levels of the 2 nd. ADC is incre- ased to avoid the use of an analog delay circuit, it can be said that the circuitry offers a considerable reduction in the number of circuit ele· ments as compared with an 8 bit all parallel device (255 to 69 circuit units). ACKNOWLEDGEMENT The auther wishes to express his sineere thanks to Prof. F. Paschke, Prof. F. Seifert and Prof. H.W. Pötzl of the Technical University of Vienna, Austria, for initiating this work and for many valuable discussions. REFERENCES 1· P.H. SAUL, A. FAIRGRIEVE and A.J. FRYERS, "Monolithic Components for 100 MHz Data Conversion", IEEE Journal of Solid-State Circuits, Vol. SC-15, No-3, June 1980, pp. 286-290. 2- "SDA 5010 AD Converter, 6 bit, DC-100 MHz", Siemens Product Profilo, 1980. 3· M. AUER, "Auswirkungen des Einsatzes von Stromspiegeln auf die Schalt- zeiten von ECL-Strukturen", Nachrichtentechnik-Elektronik, H. 12, s. 505- 509,1978. -- 6-